1. Field of the Invention
The present invention relates to forming a shaped floating gate. More particularly, the present invention relates to fabricating a floating gate semiconductor device with reduced erase voltage.
2. Description of the Related Art
A nonvolatile memory device is one that retains its information even when power is removed from the circuit. A metal oxide semiconductor (MOS) transistor is typically used for this purpose. One such structure consists of a MOS transistor with a stacked polysilicon gate structure.
Referring to FIG. 1, a cross-sectional view of a memory cell 102 with a conventional stacked polysilicon gate structure is presented. The memory cell 102 includes a source diffusion region 104, a drain diffusion region 106, and a stacked gate structure. The stacked gate structure includes an upper electrode 108 that serves as a control gate and a lower electrode 110 that serves as a floating gate. The memory cell may further include dielectric regions 112. Memory cells are typically separated by a field oxide isolation 114.
To program the memory cell, a positive voltage is applied to the control gate 108. In response to this applied voltage, a first channel 116 is created beneath the control gate 108. If the source 104 is grounded and a voltage is applied to the drain 106, a second channel 118 is created beneath the floating gate 110. Thus, an increased electrical field is created at the junction between the first channel 116 and the second channel 118, and the memory cell 102 is programmed when electrons are injected into the floating gate 110. As shown, the channels 116, 118 formed in such a device are disposed horizontally. As a result, the channel length required for functionality of the device must be realized in the horizontal dimensions of the device.
While such flash EPROM devices can be programmed at reasonably low voltages, erasure of each memory cell is accomplished through Fowler-Nordheim tunneling, and therefore requires high electric fields. This requirement in combination with the minimum thickness of the dielectric required to ensure data retention, translates into high operating voltages. Typically, to erase the memory cell 102, a large negative potential is applied to the control gate 108 with respect to the source 104 diffusion region which may be grounded. Thus, the memory cell 102 is erased when electrons are ejected out of the floating gate 110. However, it would be desirable if a memory cell such as a flash EPROM device could be manufactured with a reduced erase voltage. Such a reduction of the voltage required to erase a memory cell may be accomplished through enhancing the electric field for a given voltage.
One method for enhancing the electric field for a given voltage and a given tunnel dielectric thickness is to provide an injector shaped in such a way as to locally enhance the electric field. The formation of such a shaped floating gate is disclosed in U.S. Pat. No. 5,029,130 and illustrated generally in FIG. 2. The device 202 is formed on a semiconductor substrate 204 and includes a source diffusion region 206 and a drain diffusion region 208. As shown, the shaped floating gate 210 includes a field-enhancing edge tipped upwards, facing the control gate 212. The floating gate 210 and the control gate 212 are separated by a dielectric layer 214. The method for forming such a structure includes deposition of a floating gate polysilicon. This floating gate polysilicon is then capped with nitride. An aperture is then opened in the nitride. The shape of the floating gate polysilicon is then modified at the edges of the aperture through the formation of a xe2x80x9cbird""s beakxe2x80x9d after a conventional LOCOS (local oxidation) Field Oxidation Process. The nitride and floating gate polysilicon are then etched aligned to the silicon dioxide grown during the LOCOS Field Oxidation Process. However, this disclosed method provides geometrical limitations, since the process requires a minimum nitride opening. Similarly, the oxidation produces a minimum lateral curvature. Accordingly, such a method does not allow for downscaling of a memory cell in sub-micron processes.
In view of the above, a need exists in the prior art for a memory cell with a reduced erase voltage. Moreover, it would be beneficial if a shaped floating gate were fabricated which would allow for downscaling of the cell in sub-micron processes.
The present invention provides a shaped floating gate. This is accomplished through etching a trench in a surface of an integrated circuit substrate and forming a shaped floating gate that fills the trench. As a result, the shaped floating gate includes a bottom portion that points away from the control gate. Accordingly, the shaped floating gate may be used in a semiconductor device such as a flash EPROM device to enhance the electric field for a given voltage, reducing the voltage required to erase a memory cell.
In accordance with one aspect of the present invention, a method for forming a shaped floating gate on an integrated circuit substrate includes etching a trench in a surface of the integrated circuit substrate. The trench includes a tip that may be defined by a first sidewall and a second sidewall. By way of example, the first sidewall may be approximately perpendicular to the surface of the integrated circuit substrate while the second sidewall may be disposed at an angle to the surface of the integrated circuit substrate. A dielectric layer is formed over the substrate surface and conforming to the trench. A conductive layer is then deposited above the dielectric layer such that it fills the trench. The conductive layer is then etched such that a floating gate is defined. Upon completion of the conductive layer etching step, a bottom portion of the floating gate is contained by the trench. A semiconductor device including the shaped floating gate may then be fabricated.
In accordance with another aspect of the present invention, a semiconductor device includes a diffusion region disposed in an integrated circuit substrate. The substrate surface defines a trench forming a tip that points into the diffusion region. By way of example, the tip may be defined by a first sidewall and a second sidewall. A dielectric layer is disposed above a surface of the integrated circuit substrate surface. A floating gate is formed above the dielectric layer such that the floating gate includes a field enhancing tip contained by the tip of the trench. The dielectric layer forms a dielectric region that is adjacent to the trench and adapted for promoting capacitive coupling between the floating gate and the diffusion region. By way of example, the dielectric region may include a vertically disposed dielectric region adjacent to a first sidewall. As a result, the tip of the floating gate serves as an injector to locally enhance the electric field for a given voltage. Accordingly, the floating gate may be implemented in a memory device such as a flash EPROM to reduce the erase voltage required.
The advantages of the present invention are numerous. Through the placement of a vertically disposed trench region between the shaped floating gate and a high voltage diffusion region, capacitive coupling between the high diffusion region and the floating gate is promoted. Accordingly, the shaped floating gate serves as an injector to enhance the electric field at the tip of the floating gate. Since the electric field is enhanced for a given voltage, the voltage required to erase an EPROM device is reduced. As a result, an integrated circuit containing the present invention consumes minimal power and therefore provides reduced operating costs. Moreover, the shaped floating gate and semiconductor device are scalable, and therefore effective at small geometries to accommodate sub-micron IC feature sizes.